tag: verification

HW Security: A Hybrid Verification Method Combining Simulation And Formal Verification (RPTU, UCSD)
By Technical Paper Link - 01 Jul, 2025 - Comments: 0

A new technical paper titled "FastPath: A Hybrid Approach for Efficient Hardware Security Verification" was published by researchers at RPTU Kaiserslautern-Landau and UC San Diego. "We propose FastPath, a hybrid verification methodology that combines the efficiency of simulation with the exhaustive nature of formal verification. FastPath employs a structural analysis framework to automate th... » read more

Rethinking Chip Debug
By Priyank Jain - 30 Jun, 2025 - Comments: 0

The semiconductor industry has spent decades mastering the art of integrated circuit physical verification. But as system-on-chip (SoC) designs push the boundaries of complexity—with more transistors, greater integration and larger silicon areas—the established debug strategies are breaking under the weight of scale. Today’s advanced chips can generate an overwhelming number of design rul... » read more

Iteration And Hallucination
By Brian Bailey - 26 Jun, 2025 - Comments: 0

Iteration loops have been a vital aspect of EDA flows for decades. Ever since gate delays and wire delays became comparable, it became necessary to find out if the result of a given logic synthesis run would yield acceptable timing. Over the years this problem became worse because one decision can affect many others. The ramifications of a decision may not have been obvious to an individual too... » read more

Security Vulnerabilities Difficult To Detect In Verification Flow
By Ann Mutschler - 26 Jun, 2025 - Comments: 0

As designs grow in complexity and size, the landscape for potential hackers to infiltrate a chip at any point in either the design or verification flow increases commensurately. Long considered to be a “safe” aspect of the design process, verification now must be a focus of chip developers from a security perspective. This also means the concept of trust has never been higher, and the tr... » read more

A Guide To SDC-Based Timing Intent Verification With Questa One
By Siemens EDA - 16 Jun, 2025 - Comments: 0

As semiconductor designs continue to grow in complexity and timing margins become increasingly constrained, achieving predictable timing closure has evolved from a best practice into a critical requirement for first-pass silicon success. At the heart of this process lies the timing constraint file, i.e., the SDC (Synopsys Design Constraints), which defines the intended timing behavior of the de... » read more

Smarter, Faster, Leaner: Rethinking Verification For The Modern Era
By Harry Foster - 12 Jun, 2025 - Comments: 0

Verification isn’t just another step in the semiconductor design process—it’s increasingly the step that defines whether teams hit their schedules or miss the mark. With skyrocketing design complexity, accelerated development timelines, and persistent engineering shortages, the industry is feeling the pressure. Traditional methods aren’t keeping pace. At Siemens, we’ve been rethink... » read more

Verification Software And Methodology Insights
By Robbie O'Sullivan - 12 Jun, 2025 - Comments: 0

Earlier this month, I had the opportunity to attend CadenceLIVE Silicon Valley 2025. Among the many engaging sessions, the Verification Software track highlighted how leading companies are advancing verification methodologies to meet the demands of increasingly complex designs. The track featured seven presentations from industry leaders, each offering a unique perspective on how SVG’s verif... » read more

Agentic AI In Chip Design
By Ann Mutschler - 11 Jun, 2025 - Comments: 1

Large language models (LLMs) like ChatGPT are just the starting point for generating content with AI. The next phase will be about harnessing LLMs with agents, providing automated feedback and improvements in performance and accuracy. Mehir Arora, backend engineer at ChipAgents, talks about the impact this can have on EDA and chip design, allowing smaller teams to compete with larger teams, and... » read more

Closing The RISC-V Verification Disconnect
By Larry Lapides - 29 May, 2025 - Comments: 0

With the explosive adoption of RISC-V processors, processor verification has become a hot topic. This is due both to the criticality of the processor IP in the SoC and to the fact that many experienced SoC verification engineers are doing their first processor verification project. While there are similarities between SoC verification and processor verification, there are also significant diffe... » read more

A Balanced Approach To Verification
By Brian Bailey - 29 May, 2025 - Comments: 1

First-time chip success rates are dropping, primarily due to increased complexity and attempts to cut costs. That means management must take a close look at their verification strategies to determine if they are maximizing the potential of their tools and staff. Using simulation to demonstrate that a design exhibits a required behavior has been the cornerstone of functional verification sinc... » read more

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